Segcache: a memory-efficient and scalable in-memory key-value cache for small objects

Related tags

Deep Learning Segcache
Overview

Segcache: a memory-efficient and scalable in-memory key-value cache for small objects

This repo contains the code of Segcache described in the following paper:

Repository structure

Usage

Requirement

  • platform: Mac OS X or Linux
  • build tools: cmake (>=2.8)
  • compiler: gcc (>=4.8) or clang (>=3.1)
  • (optional) unit testing framework: check (>=0.10.0). See below.

Build

git clone https://github.com/Thesys-lab/Segcache.git
mkdir _build && cd _build
cmake ..
make -j

The executables can be found under _bin/ (under build directory)

To run all the tests, including those on ccommon, run:

make test

To skip building tests, replace the cmake step with the following:

cmake -DCHECK_WORKING=off ..

Run benchmarks

After building, you should have _build/bin/trace_replay_seg and _build/bin/trace_replay_slab which are the benchmarks for Segcache and Pelikan_twemcache. To run them, you can do

./trace_replay_slab trace_replay_slab.conf
./trace_replay_seg trace_replay_seg.conf

We provide example config to run the two benchmarks at benchmarks/config/examples/. Before using it, you need to change the options, specifically, you need to change trace_path to the path of your trace.

We release the five traces we use here. The traces are comparessed with zstd, you can use

zstd -d c.sbin.zst

to decompress, the raw traces are in binary format and can be directly consumed by the benchmark.

If you would like to use your traces, you can convert your trace into the following format, each request uses 20 bytes with the following format

struct request {
    uint32_t real_time, 
    uint64_t obj_id, 
    uint32_t key_size:8, 
    uint32_t val_size:24,
    uint32_t op:8,
    uint32_t ttl:24
};

License

This software is licensed under the Apache 2.0 license, see LICENSE for details.

Comments
  • Can I put in another cache algorithm?

    Can I put in another cache algorithm?

    Hello, I received the explanation of the Fig I answered last time.

    There is one more thing I want to do. I want to add FIFO and LRU to experiment, where should I attach the code and what should I modify?

    opened by gwanil 16
  • Hi, some questions about scalability?

    Hi, some questions about scalability?

    Here is my config:

    debug_logging: yes debug_log_level: 4 trace_path: /home/newstu/Segcache/traces/c.sbin default_ttl_list: 86400:0.65,1296000:0.27,43200:0.07 heap_mem: 1048576000 hash_power: 26 seg_evict_opt: 2 n_thread:4 seg_n_thread:1

    Does it mean that I need to copy four identical files named sbin0, sbin1, sbin2, and sbin3, which have the same content; or do I need to make some division of a sbin file into four files?

    opened by Yemaoxin 14
  • Segmentation fault happened when seg_evict_opt=5 and seg_n_merge=2

    Segmentation fault happened when seg_evict_opt=5 and seg_n_merge=2

    I set the seg_evict_opt to 5 (merge fifo) and seg_n_merge to 2. Under the workload c.sbin, a Segment fault happened with some asserts, shown as below.

    [main] assert 'seg_id != -1' failed @ (/home/aim/hdk/test/Segcache/src/storage/seg/seg.c, 177) [main] assert 'seg->accessible == 0' failed @ (/home/aim/hdk/test/Segcache/src/storage/seg/seg.c, 191) [main] assert 'seg->evictable == 0' failed @ (/home/aim/hdk/test/Segcache/src/storage/seg/seg.c, 192) [main] assert 'new_seg->evictable == 0' failed @ (/home/aim/hdk/test/Segcache/src/storage/seg/segmerge.c, 543) [main] assert 'tb->first_seg_id == old_seg_id' failed @ (/home/aim/hdk/test/Segcache/src/storage/seg/segmerge.c, 163) [main] assert 'ttl_bucket->last_seg_id == -1' failed @ (/home/aim/hdk/test/Segcache/src/storage/seg/ttlbucket.c, 109)

    When I set seg_n_merge to 3, Segcache can execute successfully.

    opened by daokunhu 9
  • Questions about adding LRU and FIFO

    Questions about adding LRU and FIFO

    Hello You told me that I can modify the LHD code if I want to experiment by adding the LUR and FIFO in the way you answered me last time, so can I modify the code at the location below?

    https://github.com/Thesys-lab/Segcache/blob/NSDI21/src/storage/LHD/LHD.h

    I don't know how to modify lru and Fifio well Would you be able to help me?

    opened by gwanil 6
  • Questions about the configuration of the experiment

    Questions about the configuration of the experiment

    I want to experiment with the experiment in Figure 6. To do that, it seems that we need a variety of algo, so do we need to experiment with pelikan? Or should I build this source and benchmark it? Could you tell me how?

    I tried building and found trace_replay_* and there were 3 algo in total. (ㄷ(ex.LHD, slab, seg...)

    There are six ways in total, what should I do?

    opened by gwanil 4
  • Some questions about configurations in experiment setup

    Some questions about configurations in experiment setup

    Thanks for your nice work!. Could you please offer an example of the configurations in the experiment setup? Here are some concerns:

    • Large size and small size for workloads c,u1,u2,n,mix in Fig.6
    • HASH_POWER

    Besides, is there any way to print the number of merged segments after an evaluation?

    Thanks for your patience. Looking forward to your reply.

    opened by daokunhu 2
  • NO

    NO "trace_replay_seg" and "trace_replay_seg" found after building.

    After building, in build/bin there are just image

    But pelikan_segcache doesn't recognize trace_replay_seg.conf The output for "$ ./pelikan_segcache trace_replay_seg.conf" is

    load config from trace_replay_seg.conf error loading config line: no option named 'debug_logging' failed to load config

    opened by daokunhu 1
  • trace_replay_seg error

    trace_replay_seg error

    An error occurs as shown in the picture below. An error occurs only when you run mix1 among the traces you downloaded, and the rest works well. What's the reason?

    22222222222222222

    44444444444444444

    opened by gwanil 2
  • Question about replaying traces

    Question about replaying traces

    Hi,

    While evaluating the performance of Twitter Memcached, I am wondering whether there is a client-side load generator that can replay the traces. The provided trace replayer is enough for exploring the cache hit and miss ratio. I think, however, it is insufficient for measuring performance numbers such as tail latency because it does not model the inter-arrival rate between requests.

    Thanks in advance!

    opened by Jeongseob 5
Owner
TheSys Group @ CMU CS
Prof. Rashmi Vinayak's research group
TheSys Group @ CMU CS
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