VHDL to Discrete Logic on PCB Flow

Overview

PCBFlow

Highly experimental set of scripts to transform a digital circuit described in a hardware description language (VHDL or Verilog) into a discrete transistor circuit on a PCB. (Disclaimer: I don't know what I am doing)

Makes use of:

  • GHDL
  • Yosys
  • ABC
  • GTKView
  • NGspice
  • PCBPlace - my own P&R tool written in Python
  • Freerouting (Optional)
  • Eagle (Optional)
  • EasyEDA (Optional)

Should work in a Linux shell. I am currently using WSL2.

For details see Project logs on HaD.io

Flow Architecture

Flow Architecture

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Comments
  • no SUBCKT if loading from verilog instead of GHDL

    no SUBCKT if loading from verilog instead of GHDL

    I slightly modified one of the provided flows to replace the GHDL step with:

    read_verilog -sv -formal ../main.sv ../vinclude/*.sv
    hierarchy -check -top Mover
    proc
    

    but the generated spice will not contain any SUBCKTs, which PCBPlace dies about. any ideas?

    the code at the time of writing this issue is available in this commit, executed from the sim/pcb/ folder with this command: yosys flow_discrete_LTL.ys

    opened by nonchip 7
  • Keep track of merged net assignment to allows merging multiple connected nets

    Keep track of merged net assignment to allows merging multiple connected nets

                                                    # TODO: Keep track of merged net assignment to allows merging multiple connected nets
    

    https://github.com/cpldcpu/PCBFlow/blob/881925be87ee0536a80e3b9b6c9fd37e241011a7/30_PLACE/PCBPlace.py#L780

    opened by cpldcpu 0
  • PCB Placement: Could not insert I/O cell in line zero

    PCB Placement: Could not insert I/O cell in line zero

    Hi, I tried to use PCBFlow on a VHDL design of mine. In particular, it is a complex adder(my implementation of the Pentium 4 Adder). After some trial and error I've successfully completed phases 10 (HDL Analysis) and 20 (Synthesis). The synthesis has been performed with the standard RT logic. The problem comes in the placement: when I try to launch the bash script for the placement, the PCBPlace.py script return this error:

    Exception during parsing of input file '209_synthesized_output.sp' Conflicting line: '.SUBCKT carryselectblock_4 op1.0 op1.1 op1.2 op1.3 op2.0 op2.1 op2.2 op2.3 cin o.0 o.1 o.2 o.3' Exception message: Could not insert I/O cell in line zero! Please increase the X-width of the cell array or correct FixedIO assignment.

    I've tried digging a bit around but with my limited SPICE knowledge I couldn't figure out a proper solution. I'm leaving in the attachment the synthesised SPICE and JSON netlists (I changed the extension from .sp and .json to .txt otherwise GitHub wouldn't let me upload it), resulting from Yosys synthesis as I think can be of help. Please let me know if I can help in some way debugging the code or figuring out where the issue could be.

    209_synthesized_output.json.txt 209_synthesized_output.sp.txt

    opened by mkexc 9
Owner
Tim
Tim
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