Hi,
I tried to use PCBFlow on a VHDL design of mine. In particular, it is a complex adder(my implementation of the Pentium 4 Adder).
After some trial and error I've successfully completed phases 10 (HDL Analysis) and 20 (Synthesis).
The synthesis has been performed with the standard RT logic.
The problem comes in the placement: when I try to launch the bash script for the placement, the PCBPlace.py script return this error:
Exception during parsing of input file '209_synthesized_output.sp'
Conflicting line: '.SUBCKT carryselectblock_4 op1.0 op1.1 op1.2 op1.3 op2.0 op2.1 op2.2 op2.3 cin o.0 o.1 o.2 o.3'
Exception message: Could not insert I/O cell in line zero! Please increase the X-width of the cell array or correct FixedIO assignment.
I've tried digging a bit around but with my limited SPICE knowledge I couldn't figure out a proper solution.
I'm leaving in the attachment the synthesised SPICE and JSON netlists (I changed the extension from .sp and .json to .txt otherwise GitHub wouldn't let me upload it), resulting from Yosys synthesis as I think can be of help.
Please let me know if I can help in some way debugging the code or figuring out where the issue could be.
209_synthesized_output.json.txt
209_synthesized_output.sp.txt